arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts
Extension
.dts
Size
1827 bytes
Lines
84
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/dts-v1/;

#include "rk3568-hinlink-opc.dtsi"

/ {
	model = "HINLINK H68K";
	compatible = "hinlink,h68k", "rockchip,rk3568";

	aliases {
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
	};
};

&gmac0 {
	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
	assigned-clock-rates = <0>, <125000000>;
	clock_in_out = "output";
	phy-handle = <&rgmii_phy0>;
	phy-mode = "rgmii-id";
	phy-supply = <&vcc3v3_sys>;
	pinctrl-names = "default";
	pinctrl-0 = <&gmac0_miim
		     &gmac0_tx_bus2
		     &gmac0_rx_bus2
		     &gmac0_rgmii_clk
		     &gmac0_rgmii_bus
		     &gmac0_rstn>;
	status = "okay";
};

&gmac1 {
	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
	assigned-clock-rates = <0>, <125000000>;
	clock_in_out = "output";
	phy-handle = <&rgmii_phy1>;
	phy-mode = "rgmii-id";
	phy-supply = <&vcc3v3_sys>;
	pinctrl-names = "default";
	pinctrl-0 = <&gmac1m1_miim
		     &gmac1m1_tx_bus2
		     &gmac1m1_rx_bus2
		     &gmac1m1_rgmii_clk
		     &gmac1m1_rgmii_bus
		     &gmac1_rstn>;
	status = "okay";
};

&mdio0 {
	rgmii_phy0: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x1>;
		reset-assert-us = <20000>;
		reset-deassert-us = <100000>;
		reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
	};
};

&mdio1 {
	rgmii_phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x1>;
		reset-assert-us = <20000>;
		reset-deassert-us = <100000>;
		reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
	};

Annotation

Implementation Notes