arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso
Extension
.dtso
Size
1257 bytes
Lines
57
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: arch/arm64
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
 *
 * DT-overlay for Edgeble On-SoM WiFi6/BT M.2 1216 modules,
 * - AW-XM548NF
 * - Intel 8260D2W
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>

&{/} {
	vcc3v3_pcie2x1l1: regulator-vcc3v3-pcie2x1l1 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; /* WIFI_3V3_EN */
		pinctrl-names = "default";
		pinctrl-0 = <&pcie2_1_vcc3v3_en>;
		regulator-name = "vcc3v3_pcie2x1l1";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <50000>;
		vin-supply = <&vcc5v0_sys>;
	};
};

&combphy2_psu {
	status = "okay";
};

/* WiFi6 */
&pcie2x1l1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie2_1_rst>;
	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; /* PCIE20_2_WIFI_PERSTn */
	vpcie3v3-supply = <&vcc3v3_pcie2x1l1>;
	status = "okay";
};

&pinctrl {
	pcie2 {
		pcie2_1_rst: pcie2-1-rst {
			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		pcie2_1_vcc3v3_en: pcie2-1-vcc-en {
			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

Annotation

Implementation Notes