arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso- Extension
.dtso- Size
- 620 bytes
- Lines
- 30
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: arch/arm64
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode
* in the SRNS (Separate Reference Clock No Spread) configuration.
*
* NOTE: If using a setup with two ROCK 5B:s, with one board running in
* RC mode and the other board running in EP mode, see also the device
* tree overlay: rk3588-rock-5b-pcie-srns.dtso.
*/
/dts-v1/;
/plugin/;
&pcie30phy {
rockchip,rx-common-refclk-mode = <0 0 0 0>;
};
&pcie3x4 {
status = "disabled";
};
&pcie3x4_ep {
vpcie3v3-supply = <&vcc3v3_pcie30>;
status = "okay";
};
&mmu600_pcie {
status = "disabled";
};
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.