arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi- Extension
.dtsi- Size
- 15731 bytes
- Lines
- 674
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.hdt-bindings/gpio/uniphier-gpio.hdt-bindings/interrupt-controller/arm-gic.huniphier-pinctrl.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD11 SoC
//
// Copyright (C) 2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-ld11";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
cluster0_opp: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-245000000 {
opp-hz = /bits/ 64 <245000000>;
clock-latency-ns = <300>;
};
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`, `dt-bindings/gpio/uniphier-gpio.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `uniphier-pinctrl.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.