arch/arm64/boot/dts/sophgo/sg2000.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/sophgo/sg2000.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/sophgo/sg2000.dtsi- Extension
.dtsi- Size
- 1899 bytes
- Lines
- 87
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.hriscv/sophgo/cv180x.dtsiriscv/sophgo/cv181x.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <riscv/sophgo/cv180x.dtsi>
#include <riscv/sophgo/cv181x.dtsi>
/ {
compatible = "sophgo,sg2000";
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
i-cache-size = <32768>;
d-cache-size = <32768>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x20000>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512MiB */
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
cpu_on = <0xc4000003>;
cpu_off = <0x84000002>;
};
soc {
gic: interrupt-controller@1f01000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x01f01000 0x1000>,
<0x01f02000 0x2000>;
};
pinctrl: pinctrl@3001000 {
compatible = "sophgo,sg2000-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
clk: clock-controller@3002000 {
compatible = "sophgo,sg2000-clk";
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `riscv/sophgo/cv180x.dtsi`, `riscv/sophgo/cv181x.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.