arch/arm64/boot/dts/synaptics/berlin4ct.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
Extension
.dtsi
Size
6843 bytes
Lines
317
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2015 Marvell Technology Group Ltd.
 *
 * Author: Jisheng Zhang <jszhang@marvell.com>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "marvell,berlin4ct", "marvell,berlin";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x1>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x2>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x3>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		l2: cache {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};

Annotation

Implementation Notes