arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-can.dtso

File Facts

System

Linux kernel

Corpus path

arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-can.dtso

Extension

.dtso

Size

669 bytes

Lines

29

Domain

Architecture Layer

Bucket

arch/arm64

Inferred role

Architecture Layer: arch/arm64

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• k3-pinctrl.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (c) Toradex
 *
 * Enable AM62 MCU_MCAN1 exposed on Toradex Verdin Development Board with
 * Verdin AM62 Mezzanine expansion board on CAN Header (J13),
 * Pin 3 (CAN1_CONN_N) and Pin 4 (CAN1_CONN_P).
 */

/dts-v1/;
/plugin/;

#include "k3-pinctrl.h"

&mcu_pmx0 {
	pinctrl_mcu_mcan1: mcu-mcan1-default-pins {
		pinctrl-single,pins = <
			AM62X_MCU_IOPAD(0x0040, PIN_INPUT,  0) /* (D4) MCU_MCAN1_RX (SODIMM 116) */
			AM62X_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX (SODIMM 128) */
		>;
	};
};

&mcu_mcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mcu_mcan1>;
	status = "okay";
};

Annotation

• Immediate include surface: `k3-pinctrl.h`.
• Atlas domain: Architecture Layer / arch/arm64.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.