arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi- Extension
.dtsi- Size
- 5662 bytes
- Lines
- 204
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
*
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
mcu_pmx0: pinctrl@4084000 {
compatible = "pinctrl-single";
reg = <0x00 0x04084000 0x00 0x88>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
mcu_esm: esm@4100000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x4100000 0x0 0x1000>;
bootph-pre-ram;
/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */
ti,esm-pins = <0>, <1>, <2>, <85>;
};
/*
* The MCU domain timer interrupts are routed only to the ESM module,
* and not currently available for Linux. The MCU domain timers are
* of limited use without interrupts, and likely reserved by the ESM.
*/
mcu_timer0: timer@4800000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4800000 0x00 0x400>;
clocks = <&k3_clks 35 2>;
clock-names = "fck";
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer1: timer@4810000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4810000 0x00 0x400>;
clocks = <&k3_clks 48 2>;
clock-names = "fck";
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer2: timer@4820000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4820000 0x00 0x400>;
clocks = <&k3_clks 49 2>;
clock-names = "fck";
power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer3: timer@4830000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4830000 0x00 0x400>;
clocks = <&k3_clks 50 2>;
clock-names = "fck";
power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_uart0: serial@4a00000 {
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.