arch/arm64/boot/dts/ti/k3-am62l.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am62l.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-am62l.dtsi- Extension
.dtsi- Size
- 4338 bytes
- Lines
- 120
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.hdt-bindings/interrupt-controller/irq.hdt-bindings/interrupt-controller/arm-gic.hk3-pinctrl.hk3-am62l-main.dtsik3-am62l-wakeup.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only or MIT
/*
* Device Tree Source for AM62L SoC Family
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
*
* Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "k3-pinctrl.h"
/ {
model = "Texas Instruments K3 AM62L3 SoC";
compatible = "ti,am62l3";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
scmi: scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0x82004000>;
shmem = <&scmi_shmem>;
#address-cells = <1>;
#size-cells = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
bootph-all;
};
scmi_pds: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
bootph-all;
};
};
};
a53_timer0: timer-cl0-cpu0 {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
cbass_main: bus@f0000 {
compatible = "simple-bus";
ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */
<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First Peripheral Window */
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`, `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `k3-pinctrl.h`, `k3-am62l-main.dtsi`, `k3-am62l-wakeup.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.