arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi- Extension
.dtsi- Size
- 1487 bytes
- Lines
- 63
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree file for the AM62P MAIN domain peripherals
*
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
usbss1: usb@f910000 {
compatible = "ti,am62-usb";
reg = <0x00 0x0f910000 0x00 0x800>,
<0x00 0x0f918000 0x00 0x400>;
clocks = <&k3_clks 162 3>;
clock-names = "ref";
ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
#address-cells = <2>;
#size-cells = <2>;
power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
ranges;
status = "disabled";
usb1: usb@31100000 {
compatible = "snps,dwc3";
reg = <0x00 0x31100000 0x00 0x50000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
snps,usb2-gadget-lpm-disable;
snps,usb2-lpm-disable;
};
};
};
&oc_sram {
reg = <0x00 0x70000000 0x00 0x10000>;
ranges = <0x00 0x00 0x70000000 0x10000>;
};
&inta_main_dmss {
ti,interrupt-ranges = <5 69 35>;
};
&main_gpio0 {
gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
<&main_pmx0 70 72 22>;
ti,ngpio = <92>;
};
&main_gpio1 {
gpio-ranges = <&main_pmx0 0 94 32>, <&main_pmx0 42 137 5>,
<&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
gpio-reserved-ranges = <32 10>;
ti,ngpio = <52>;
};
&sdhci0 {
mmc-hs400-1_8v;
ti,strobe-sel = <0x66>;
ti,otap-del-sel-hs400 = <0x5>;
};
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.