arch/arm64/boot/dts/ti/k3-am62p5.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am62p5.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/ti/k3-am62p5.dtsi
Extension
.dtsi
Size
3297 bytes
Lines
159
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree file for the AM62P5 SoC family (quad core)
 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
 *
 * TRM: https://www.ti.com/lit/pdf/spruj83
 */

/dts-v1/;

#include "k3-am62p.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0: cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			reg = <0x000>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			operating-points-v2 = <&a53_opp_table>;
			clocks = <&k3_clks 135 0>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			operating-points-v2 = <&a53_opp_table>;
			clocks = <&k3_clks 136 0>;
			#cooling-cells = <2>;
		};

Annotation

Implementation Notes