arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi- Extension
.dtsi- Size
- 11164 bytes
- Lines
- 436
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.hdt-bindings/input/input.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/leds/common.hdt-bindings/pwm/pwm.hk3-am62p5.dtsik3-am62p-ti-ipc-firmware.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Common dtsi for Variscite VAR-SOM-AM62P
*
* Link: https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
*
* Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
#include "k3-am62p5.dtsi"
/ {
compatible = "variscite,var-som-am62p", "ti,am62p5";
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
<&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
};
mmc_pwrseq: mmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc_pwrseq>;
reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
};
memory@80000000 {
/* 8G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000001 0x80000000>;
device_type = "memory";
bootph-pre-ram;
};
opp-table {
/* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-supported-hw = <0x01 0x0004>;
clock-latency-ns = <6000000>;
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9b500000 0x00 0x00300000>;
no-map;
};
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9c800000 0x00 0x00100000>;
no-map;
};
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`, `dt-bindings/input/input.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/leds/common.h`, `dt-bindings/pwm/pwm.h`, `k3-am62p5.dtsi`, `k3-am62p-ti-ipc-firmware.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.