arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi- Extension
.dtsi- Size
- 15543 bytes
- Lines
- 507
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/net/ti-dp83869.hk3-am64-ti-ipc-firmware.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
*
*/
#include <dt-bindings/net/ti-dp83869.h>
/ {
model = "SolidRun AM642 SoM";
compatible = "solidrun,am642-sr-som", "ti,am642";
aliases {
ethernet0 = &cpsw_port1;
ethernet1 = &icssg1_emac0;
ethernet2 = &icssg1_emac1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
serial2 = &main_uart0;
};
chosen {
/* SoC default UART console */
stdout-path = "serial2:115200n8";
};
/* PRU Ethernet Controller */
ethernet {
compatible = "ti,am642-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>;
sram = <&oc_sram>;
ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
/* configure internal pinmux for mii mode */
ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>;
ti,mii-g-rt = <&icssg1_mii_g_rt>;
ti,mii-rt = <&icssg1_mii_rt>;
ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
/*
* Configure icssg interrupt controller to map pru-internal
* interrupts 8/9 via channels 0/1 to host interrupts 0/1.
*
* For details see interrupt controller documentation:
* Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
*/
interrupt-parent = <&icssg1_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
<&main_pktdma 0xc201 15>, /* egress slice 0 */
<&main_pktdma 0xc202 15>, /* egress slice 0 */
<&main_pktdma 0xc203 15>, /* egress slice 0 */
<&main_pktdma 0xc204 15>, /* egress slice 1 */
<&main_pktdma 0xc205 15>, /* egress slice 1 */
<&main_pktdma 0xc206 15>, /* egress slice 1 */
<&main_pktdma 0xc207 15>, /* egress slice 1 */
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
<&main_pktdma 0x4201 15>; /* ingress slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
Annotation
- Immediate include surface: `dt-bindings/net/ti-dp83869.h`, `k3-am64-ti-ipc-firmware.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.