arch/arm64/boot/dts/ti/k3-am65.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am65.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/ti/k3-am65.dtsi
Extension
.dtsi
Size
3977 bytes
Lines
109
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for AM6 SoC Family
 *
 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>

#include "k3-pinctrl.h"

/ {
	model = "Texas Instruments K3 AM654 SoC";
	compatible = "ti,am654";
	interrupt-parent = <&gic500>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci: psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	a53_timer0: timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
	};

	pmu: pmu {
		compatible = "arm,cortex-a53-pmu";
		/* Recommendation from GIC500 TRM Table A.3 */
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	cbass_main: bus@100000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
			 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
			 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
			 /* MCUSS Range */
			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,

Annotation

Implementation Notes