arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi

File Facts

System

Linux kernel

Corpus path

arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi

Extension

.dtsi

Size

668 bytes

Lines

28

Domain

Architecture Layer

Bucket

arch/arm64

Inferred role

Architecture Layer: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) Siemens AG, 2024
 *
 * Authors:
 *   Jan Kiszka <jan.kiszka@siemens.com>
 *
 * Common bits for IOT2050 variants with USB3 support
 */

&serdes0 {
	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
	assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
};

&dwc3_0 {
	assigned-clock-parents = <&k3_clks 151 4>,  /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
				 <&k3_clks 151 8>;  /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
	phys = <&serdes0 PHY_TYPE_USB3 0>;
	phy-names = "usb3-phy";
};

&usb0 {
	maximum-speed = "super-speed";
	snps,dis-u1-entry-quirk;
	snps,dis-u2-entry-quirk;
};

Annotation

• Atlas domain: Architecture Layer / arch/arm64.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.