arch/arm64/boot/dts/ti/k3-am654-idk.dtso
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-am654-idk.dtso- Extension
.dtso- Size
- 12450 bytes
- Lines
- 356
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: arch/arm64
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.hdt-bindings/net/ti-dp83867.hk3-pinctrl.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT overlay for IDK application board on AM654 EVM
*
* Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-pinctrl.h"
&{/} {
aliases {
ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
};
/* Ethernet node on PRU-ICSSG0 */
icssg0_eth: icssg0-eth {
compatible = "ti,am654-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&icssg0_rgmii_pins_default>;
sram = <&msmc_ram>;
ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
ti,mii-g-rt = <&icssg0_mii_g_rt>;
ti,mii-rt = <&icssg0_mii_rt>;
ti,pa-stats = <&icssg0_pa_stats>;
ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
interrupt-parent = <&icssg0_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
dmas = <&main_udmap 0xc100>, /* egress slice 0 */
<&main_udmap 0xc101>, /* egress slice 0 */
<&main_udmap 0xc102>, /* egress slice 0 */
<&main_udmap 0xc103>, /* egress slice 0 */
<&main_udmap 0xc104>, /* egress slice 1 */
<&main_udmap 0xc105>, /* egress slice 1 */
<&main_udmap 0xc106>, /* egress slice 1 */
<&main_udmap 0xc107>, /* egress slice 1 */
<&main_udmap 0x4100>, /* ingress slice 0 */
<&main_udmap 0x4101>; /* ingress slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`, `dt-bindings/net/ti-dp83867.h`, `k3-pinctrl.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.