arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso- Extension
.dtso- Size
- 539 bytes
- Lines
- 28
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: arch/arm64
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/phy/phy.hdt-bindings/gpio/gpio.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* IOT2050 M.2 variant, overlay for B-key PCIE0_LANE0 + E-key PCIE1_LANE0
* Copyright (c) Siemens AG, 2022-2024
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
&pcie0_rc {
num-lanes = <1>;
phys = <&serdes0 PHY_TYPE_PCIE 1>;
phy-names = "pcie-phy0";
reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie1_rc {
status = "okay";
};
Annotation
- Immediate include surface: `dt-bindings/phy/phy.h`, `dt-bindings/gpio/gpio.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.