arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts- Extension
.dts- Size
- 4365 bytes
- Lines
- 190
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
k3-am6548-iot2050-advanced-common.dtsik3-am65-iot2050-common-pg2.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Siemens AG, 2023
*
* Authors:
* Baocheng Su <baocheng.su@siemens.com>
* Chao Zeng <chao.zeng@siemens.com>
* Huaqian Li <huaqian.li@siemens.com>
*
* AM6548-based (quad-core) IOT2050 SM variant, Product Generation 2
* 4 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
*
* Product homepage:
* https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
*/
/dts-v1/;
#include "k3-am6548-iot2050-advanced-common.dtsi"
#include "k3-am65-iot2050-common-pg2.dtsi"
/ {
compatible = "siemens,iot2050-advanced-sm", "ti,am654";
model = "SIMATIC IOT2050 Advanced SM";
memory@80000000 {
device_type = "memory";
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
};
aliases {
spi1 = &main_spi0;
};
leds {
pinctrl-0 = <&leds_pins_default>, <&user1_led_pins>;
led-2 {
gpios = <&wkup_gpio0 52 GPIO_ACTIVE_HIGH>;
};
led-3 {
gpios = <&wkup_gpio0 53 GPIO_ACTIVE_HIGH>;
};
};
};
&main_pmx0 {
main_pcie_enable_pins_default: main-pcie-enable-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01d8, PIN_OUTPUT, 7) /* (AH12) GPIO1_22 */
>;
};
main_spi0_pins: main-spi0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
>;
};
};
&main_pmx1 {
asic_spi_mux_ctrl_pin: asic-spi-mux-ctrl-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_OUTPUT, 7) /* (D21) GPIO1_86 */
Annotation
- Immediate include surface: `k3-am6548-iot2050-advanced-common.dtsi`, `k3-am65-iot2050-common-pg2.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.