arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi- Extension
.dtsi- Size
- 9452 bytes
- Lines
- 388
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.hdt-bindings/net/ti-dp83867.hk3-j721s2.dtsik3-j721s2-ti-ipc-firmware.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Dominik Haller <d.haller@phytec.de>
*
* https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-j721s2.dtsi"
/ {
compatible = "phytec,am68-phycore-som", "ti,j721s2";
model = "PHYTEC phyCORE-AM68x";
aliases {
ethernet1 = &main_cpsw_port1;
mmc0 = &main_sdhci0;
rtc0 = &i2c_som_rtc;
};
memory@80000000 {
device_type = "memory";
/* 4GB RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
bootph-all;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* global cma region */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x00 0x20000000>;
linux,cma-default;
};
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
alignment = <0x1000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
};
vdd_sd_dv: regulator-sd {
/* Output of TLV71033 */
compatible = "regulator-gpio";
regulator-name = "VDD_SD_DV";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_pins_default>;
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`, `dt-bindings/net/ti-dp83867.h`, `k3-j721s2.dtsi`, `k3-j721s2-ti-ipc-firmware.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.