arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi- Extension
.dtsi- Size
- 20132 bytes
- Lines
- 717
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
*
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
dmsc: system-controller@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes = <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x00 0x1000>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
bootph-all;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
bootph-all;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
bootph-all;
};
};
mcu_timer0: timer@40400000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40400000 0x00 0x400>;
interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 35 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 35 1>;
assigned-clock-parents = <&k3_clks 35 2>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
bootph-pre-ram;
ti,timer-pwm;
};
mcu_timer1: timer@40410000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 71 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_timer2: timer@40420000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40420000 0x00 0x400>;
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.