arch/arm64/boot/dts/ti/k3-j721e.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-j721e.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-j721e.dtsi- Extension
.dtsi- Size
- 5861 bytes
- Lines
- 177
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/irq.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/soc/ti,sci_pm_domain.hk3-pinctrl.hk3-j721e-thermal.dtsik3-j721e-main.dtsik3-j721e-mcu-wakeup.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J721E SoC Family
*
* Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/ {
model = "Texas Instruments K3 J721E SoC";
compatible = "ti,j721e";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a72";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a72";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/soc/ti,sci_pm_domain.h`, `k3-pinctrl.h`, `k3-j721e-thermal.dtsi`, `k3-j721e-main.dtsi`, `k3-j721e-mcu-wakeup.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.