arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
Extension
.dtsi
Size
65464 bytes
Lines
2251
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
 *
 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>

/ {
	serdes_refclk: clock-cmnrefclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};
};

&cbass_main {
	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x400000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x400000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};

		tifs-sram@1f0000 {
			reg = <0x1f0000 0x10000>;
		};

		l3cache-sram@200000 {
			reg = <0x200000 0x200000>;
		};
	};

	scm_conf: bus@104000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x00104000 0x18000>;

		usb_serdes_mux: mux-controller@0 {
			compatible = "reg-mux";
			reg = <0x0 0x4>;
			#mux-control-cells = <1>;
			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
		};

		phy_gmii_sel_cpsw: phy@34 {
			compatible = "ti,am654-phy-gmii-sel";
			reg = <0x34 0x4>;
			#phy-cells = <1>;
		};

		pcie1_ctrl: pcie-ctrl@74 {
			compatible = "ti,j784s4-pcie-ctrl", "syscon";
			reg = <0x74 0x4>;
		};

		serdes_ln_ctrl: mux-controller@80 {
			compatible = "reg-mux";
			reg = <0x80 0x10>;
			#mux-control-cells = <1>;
			mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
					<0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
		};

Annotation

Implementation Notes