arch/arm64/boot/dts/ti/k3-j722s-main.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
Extension
.dtsi
Size
12594 bytes
Lines
480
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree file for the J722S MAIN domain peripherals
 *
 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>

/ {
	serdes_refclk: clk-0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};
};

&cbass_main {
	serdes_wiz0: phy@f000000 {
		compatible = "ti,j722s-wiz-10g", "ti,am64-wiz-10g";
		ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		num-lanes = <1>;
		#reset-cells = <1>;
		#clock-cells = <1>;

		assigned-clocks = <&k3_clks 279 1>;
		assigned-clock-parents = <&k3_clks 279 5>;

		status = "disabled";

		serdes0: serdes@f000000 {
			compatible = "ti,j721e-serdes-10g";
			reg = <0x0f000000 0x00010000>;
			reg-names = "torrent_phy";
			resets = <&serdes_wiz0 0>;
			reset-names = "torrent_reset";
			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
			clock-names = "refclk", "phy_en_refclk";
			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
			assigned-clock-parents = <&k3_clks 279 1>,
						 <&k3_clks 279 1>,
						 <&k3_clks 279 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
		};
	};

	serdes_wiz1: phy@f010000 {
		compatible = "ti,j722s-wiz-10g", "ti,am64-wiz-10g";
		ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		num-lanes = <1>;
		#reset-cells = <1>;
		#clock-cells = <1>;

		assigned-clocks = <&k3_clks 280 1>;

Annotation

Implementation Notes