arch/arm64/boot/dts/ti/k3-j784s4.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-j784s4.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/ti/k3-j784s4.dtsi
Extension
.dtsi
Size
3425 bytes
Lines
173
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for J784S4 SoC Family
 *
 * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
 *
 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
 *
 */

#include "k3-j784s4-j742s2-common.dtsi"

/ {
	model = "Texas Instruments K3 J784S4 SoC";
	compatible = "ti,j784s4";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu-map {
			cluster0: cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1: cluster1 {
				core0 {
					cpu = <&cpu4>;
				};

				core1 {
					cpu = <&cpu5>;
				};

				core2 {
					cpu = <&cpu6>;
				};

				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&L2_0>;
		};

Annotation

Implementation Notes