arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso- Extension
.dtso- Size
- 3520 bytes
- Lines
- 141
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: arch/arm64
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.hdt-bindings/phy/phy-cadence.hdt-bindings/phy/phy.hk3-pinctrl.hk3-serdes.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>
#include "k3-pinctrl.h"
#include "k3-serdes.h"
&{/} {
aliases {
ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
};
};
&main_cpsw0 {
status = "okay";
};
&main_cpsw0_port5 {
phy-handle = <&cpsw9g_phy1>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
status = "okay";
};
&main_cpsw0_port6 {
phy-handle = <&cpsw9g_phy2>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
status = "okay";
};
&main_cpsw0_port7 {
phy-handle = <&cpsw9g_phy0>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
status = "okay";
};
&main_cpsw0_port8 {
phy-handle = <&cpsw9g_phy3>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
status = "okay";
};
&main_cpsw0_mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio0_default_pins>;
bus_freq = <1000000>;
reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <120000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`, `dt-bindings/phy/phy-cadence.h`, `dt-bindings/phy/phy.h`, `k3-pinctrl.h`, `k3-serdes.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.