arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
Extension
.dtsi
Size
5613 bytes
Lines
149
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for J784S4 and J742S2 SoC Family
 *
 * TRM (j784s4) (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
 * TRM (j742s2): https://www.ti.com/lit/pdf/spruje3
 *
 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
 *
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>

#include "k3-pinctrl.h"

/ {
	interrupt-parent = <&gic500>;
	#address-cells = <2>;
	#size-cells = <2>;

	L2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		cache-size = <0x200000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		next-level-cache = <&msmc_l3>;
	};

	L2_1: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		cache-size = <0x200000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		next-level-cache = <&msmc_l3>;
	};

	msmc_l3: l3-cache0 {
		compatible = "cache";
		cache-level = <3>;
		cache-unified;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci: psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	a72_timer0: timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
	};

	pmu: pmu {
		compatible = "arm,cortex-a72-pmu";

Annotation

Implementation Notes