arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
Extension
.dtsi
Size
78715 bytes
Lines
2716
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for J784S4 and J742S2 SoC Family Main Domain peripherals
 *
 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/mux/mux.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-ti.h>

#include "k3-serdes.h"

/ {
	serdes_refclk: clock-serdes {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* To be enabled when serdes_wiz* is functional */
		status = "disabled";
	};
};

&cbass_main {
	/*
	 * MSMC is configured by bootloaders and a runtime fixup is done in the
	 * DT for this node
	 */
	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x00 0x70000000 0x00 0x800000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x70000000 0x800000>;

		atf-sram@0 {
			reg = <0x00 0x20000>;
		};

		tifs-sram@1f0000 {
			reg = <0x1f0000 0x10000>;
		};

		l3cache-sram@200000 {
			reg = <0x200000 0x200000>;
		};
	};

	scm_conf: bus@100000 {
		compatible = "simple-bus";
		reg = <0x00 0x00100000 0x00 0x1c000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x00100000 0x1c000>;

		cpsw1_phy_gmii_sel: phy@4034 {
			compatible = "ti,am654-phy-gmii-sel";
			reg = <0x4034 0x4>;
			#phy-cells = <1>;
		};

		cpsw0_phy_gmii_sel: phy@4044 {
			compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
			reg = <0x4044 0x20>;
			#phy-cells = <1>;
			ti,qsgmii-main-ports = <7>, <7>;
		};

		pcie0_ctrl: pcie0-ctrl@4070 {
			compatible = "ti,j784s4-pcie-ctrl", "syscon";
			reg = <0x4070 0x4>;

Annotation

Implementation Notes