arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
Extension
.dtsi
Size
5030 bytes
Lines
165
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for J784S4 SoC Family Main Domain peripherals
 *
 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

&cbass_main {
	watchdog4: watchdog@2240000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x00 0x2240000 0x00 0x100>;
		clocks = <&k3_clks 352 0>;
		power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 352 0>;
		assigned-clock-parents = <&k3_clks 352 4>;
	};

	watchdog5: watchdog@2250000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x00 0x2250000 0x00 0x100>;
		clocks = <&k3_clks 353 0>;
		power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 353 0>;
		assigned-clock-parents = <&k3_clks 353 4>;
	};

	watchdog6: watchdog@2260000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x00 0x2260000 0x00 0x100>;
		clocks = <&k3_clks 354 0>;
		power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 354 0>;
		assigned-clock-parents = <&k3_clks 354 4>;
	};

	watchdog7: watchdog@2270000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x00 0x2270000 0x00 0x100>;
		clocks = <&k3_clks 355 0>;
		power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 355 0>;
		assigned-clock-parents = <&k3_clks 355 4>;
	};

	pcie2_rc: pcie@2920000 {
		compatible = "ti,j784s4-pcie-host";
		reg = <0x00 0x02920000 0x00 0x1000>,
		      <0x00 0x02927000 0x00 0x400>,
		      <0x00 0x0e000000 0x00 0x00800000>,
		      <0x44 0x00000000 0x00 0x00001000>;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 334 0>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb012>;
		msi-map = <0x0 &gic_its 0x20000 0x10000>;
		dma-coherent;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;

Annotation

Implementation Notes