arch/arm64/boot/dts/toshiba/tmpv7708.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
Extension
.dtsi
Size
13743 bytes
Lines
518
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Source for the TMPV7708
 *
 * (C) Copyright 2018 - 2020, Toshiba Corporation.
 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
 *
 */

#include <dt-bindings/clock/toshiba,tmpv770x.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x81000000 0x00300000;	/* cpu-release-addr */

/ {
	compatible = "toshiba,tmpv7708";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x81100000>;
			reg = <0x00>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x81100000>;
			reg = <0x01>;

Annotation

Implementation Notes