arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
Extension
.dtsi
Size
6051 bytes
Lines
305
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Clock specification for Xilinx ZynqMP
 *
 * (C) Copyright 2017 - 2022, Xilinx, Inc.
 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

#include "xlnx-zynqmp-clk.h"
/ {
	pss_ref_clk: pss-ref-clk {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333000>;
		clock-output-names = "pss_ref_clk";
	};

	video_clk: video-clk {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
		clock-output-names = "video_clk";
	};

	pss_alt_ref_clk: pss-alt-ref-clk {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "pss_alt_ref_clk";
	};

	gt_crx_ref_clk: gt-crx-ref-clk {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <108000000>;
		clock-output-names = "gt_crx_ref_clk";
	};

	aux_ref_clk: aux-ref-clk {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
		clock-output-names = "aux_ref_clk";
	};
};

&zynqmp_firmware {
	zynqmp_clk: clock-controller {
		bootph-all;
		#clock-cells = <1>;
		compatible = "xlnx,zynqmp-clk";
		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
			 <&aux_ref_clk>, <&gt_crx_ref_clk>;
		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
			      "aux_ref_clk", "gt_crx_ref_clk";
	};
};

&can0 {
	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&can1 {

Annotation

Implementation Notes