arch/arm64/boot/dts/xilinx/zynqmp.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/xilinx/zynqmp.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
Extension
.dtsi
Size
37767 bytes
Lines
1343
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * dts file for Xilinx ZynqMP
 *
 * (C) Copyright 2014 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "xlnx,zynqmp";
	#address-cells = <2>;
	#size-cells = <2>;

	options {
		u-boot {
			compatible = "u-boot,config";
			bootscr-address = /bits/ 64 <0x20000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			#cooling-cells = <2>;
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			operating-points-v2 = <&cpu_opp_table>;
			reg = <0x0>;
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&L2>;
		};

		cpu1: cpu@1 {
			#cooling-cells = <2>;
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x1>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&L2>;
		};

		cpu2: cpu@2 {
			#cooling-cells = <2>;
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x2>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&L2>;
		};

Annotation

Implementation Notes