arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso
Extension
.dtso
Size
7353 bytes
Lines
384
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: arch/arm64
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for KD240 revA Carrier Card
 *
 * Copyright (C) 2021 - 2022, Xilinx, Inc.
 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>

/dts-v1/;
/plugin/;

&{/} {
	compatible = "xlnx,zynqmp-sk-kd240-rev1",
		     "xlnx,zynqmp-sk-kd240-revB",
		     "xlnx,zynqmp-sk-kd240-revA",
		     "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp";
	model = "ZynqMP KD240 revA/B/1";

	aliases {
		ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */
	};

	clk_26: clock2 { /* u17 - USB */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	clk_25_0: clock4 { /* u92/u91 - GEM2 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	clk_25_1: clock5 { /* u92/u91 - GEM3 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};
};

&can0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can0_default>;
};

&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1_default>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	u3: ina260@40 { /* u3 */
		compatible = "ti,ina260";
		label = "ina260-u14";
		reg = <0x40>;
	};

	slg7xl45106: gpio@11 { /* u13 - reset logic */
		compatible = "dlg,slg7xl45106";

Annotation

Implementation Notes