arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso
Extension
.dtso
Size
9292 bytes
Lines
450
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: arch/arm64
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for KR260 revB Carrier Card (A03 revision)
 *
 * (C) Copyright 2021 - 2022, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>

/dts-v1/;
/plugin/;

&{/} {
	compatible = "xlnx,zynqmp-sk-kr260-revB",
		     "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
	model = "ZynqMP KR260 revB";

	aliases {
		ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */
		ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
	};

	clk_125: clock0 { /* u87 - GEM0/1 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
	};

	clk_27: clock1 { /* u86 - DP */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};

	clk_26: clock2 { /* u89 - USB */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	clk_156: clock3 { /* u90 - SFP+ */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <156250000>;
	};

	clk_25_0: clock4 { /* u92/u91 - GEM2 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	clk_25_1: clock5 { /* u92/u91 - GEM3 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	clk_74: clock6 { /* u88 - SLVC-EC */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <74250000>;
	};

	dpcon {

Annotation

Implementation Notes