arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
Extension
.dts
Size
8065 bytes
Lines
440
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
 *
 * (C) Copyright 2015 - 2022, Xilinx, Inc.
 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

/dts-v1/;

#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>

/ {
	model = "ZynqMP zc1751-xm015-dc1 RevA";
	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";

	aliases {
		ethernet0 = &gem3;
		i2c0 = &i2c1;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
		rtc0 = &rtc;
		serial0 = &uart0;
		spi0 = &qspi;
		usb0 = &usb0;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
	};

	clock_si5338_0: clk27 {	/* u55 SI5338-GM */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};

	clock_si5338_2: clk26 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	clock_si5338_3: clk150 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <150000000>;
	};
};

&fpd_dma_chan1 {
	status = "okay";
};

&fpd_dma_chan2 {
	status = "okay";
};

Annotation

Implementation Notes