arch/arm64/include/asm/arm_pmuv3.h
Source file repositories/reference/linux-study-clean/arch/arm64/include/asm/arm_pmuv3.h
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/include/asm/arm_pmuv3.h- Extension
.h- Size
- 3484 bytes
- Lines
- 192
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
asm/kvm_host.hasm/cpufeature.hasm/sysreg.h
Detected Declarations
function Copyrightfunction write_pmevcntrnfunction write_pmevtypernfunction read_sysregfunction read_pmmirfunction read_pmuverfunction pmuv3_has_icntrfunction write_pmcrfunction read_pmcrfunction write_pmselrfunction write_pmccntrfunction read_pmccntrfunction write_pmicntrfunction read_pmicntrfunction write_pmcntensetfunction write_pmcntenclrfunction write_pmintensetfunction write_pmintenclrfunction write_pmccfiltrfunction read_pmccfiltrfunction write_pmicfiltrfunction read_pmicfiltrfunction write_pmovsclrfunction read_pmovsclrfunction write_pmuserenrfunction write_pmuacrfunction read_pmceid0function read_pmceid1function pmuv3_implementedfunction is_pmuv3p4function is_pmuv3p5function is_pmuv3p9
Annotated Snippet
#ifndef __ASM_PMUV3_H
#define __ASM_PMUV3_H
#include <asm/kvm_host.h>
#include <asm/cpufeature.h>
#include <asm/sysreg.h>
#define RETURN_READ_PMEVCNTRN(n) \
return read_sysreg(pmevcntr##n##_el0)
static inline unsigned long read_pmevcntrn(int n)
{
PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
return 0;
}
#define WRITE_PMEVCNTRN(n) \
write_sysreg(val, pmevcntr##n##_el0)
static inline void write_pmevcntrn(int n, unsigned long val)
{
PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
}
#define WRITE_PMEVTYPERN(n) \
write_sysreg(val, pmevtyper##n##_el0)
static inline void write_pmevtypern(int n, unsigned long val)
{
PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
}
#define RETURN_READ_PMEVTYPERN(n) \
return read_sysreg(pmevtyper##n##_el0)
static inline unsigned long read_pmevtypern(int n)
{
PMEVN_SWITCH(n, RETURN_READ_PMEVTYPERN);
return 0;
}
static inline unsigned long read_pmmir(void)
{
return read_cpuid(PMMIR_EL1);
}
static inline u32 read_pmuver(void)
{
u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
return cpuid_feature_extract_unsigned_field(dfr0,
ID_AA64DFR0_EL1_PMUVer_SHIFT);
}
static inline bool pmuv3_has_icntr(void)
{
u64 dfr1 = read_sysreg(id_aa64dfr1_el1);
return !!cpuid_feature_extract_unsigned_field(dfr1,
ID_AA64DFR1_EL1_PMICNTR_SHIFT);
}
static inline void write_pmcr(u64 val)
{
write_sysreg(val, pmcr_el0);
}
static inline u64 read_pmcr(void)
{
return read_sysreg(pmcr_el0);
}
static inline void write_pmselr(u32 val)
{
write_sysreg(val, pmselr_el0);
}
static inline void write_pmccntr(u64 val)
{
write_sysreg(val, pmccntr_el0);
}
static inline u64 read_pmccntr(void)
{
return read_sysreg(pmccntr_el0);
}
static inline void write_pmicntr(u64 val)
{
write_sysreg_s(val, SYS_PMICNTR_EL0);
}
static inline u64 read_pmicntr(void)
Annotation
- Immediate include surface: `asm/kvm_host.h`, `asm/cpufeature.h`, `asm/sysreg.h`.
- Detected declarations: `function Copyright`, `function write_pmevcntrn`, `function write_pmevtypern`, `function read_sysreg`, `function read_pmmir`, `function read_pmuver`, `function pmuv3_has_icntr`, `function write_pmcr`, `function read_pmcr`, `function write_pmselr`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.