arch/arm64/include/asm/kvm_arm.h

Source file repositories/reference/linux-study-clean/arch/arm64/include/asm/kvm_arm.h

File Facts

System
Linux kernel
Corpus path
arch/arm64/include/asm/kvm_arm.h
Extension
.h
Size
11955 bytes
Lines
352
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ARM64_KVM_ARM_H__
#define __ARM64_KVM_ARM_H__

#include <asm/esr.h>
#include <asm/memory.h>
#include <asm/sysreg.h>
#include <asm/types.h>

/*
 * Because I'm terribly lazy and that repainting the whole of the KVM
 * code with the proper names is a pain, use a helper to map the names
 * inherited from AArch32 with the new fancy nomenclature. One day...
 */
#define	__HCR(x)	HCR_EL2_##x

#define HCR_TID5	__HCR(TID5)
#define HCR_DCT		__HCR(DCT)
#define HCR_ATA_SHIFT	__HCR(ATA_SHIFT)
#define HCR_ATA		__HCR(ATA)
#define HCR_TTLBOS	__HCR(TTLBOS)
#define HCR_TTLBIS	__HCR(TTLBIS)
#define HCR_ENSCXT	__HCR(EnSCXT)
#define HCR_TOCU	__HCR(TOCU)
#define HCR_AMVOFFEN	__HCR(AMVOFFEN)
#define HCR_TICAB	__HCR(TICAB)
#define HCR_TID4	__HCR(TID4)
#define HCR_FIEN	__HCR(FIEN)
#define HCR_FWB		__HCR(FWB)
#define HCR_NV2		__HCR(NV2)
#define HCR_AT		__HCR(AT)
#define HCR_NV1		__HCR(NV1)
#define HCR_NV		__HCR(NV)
#define HCR_API		__HCR(API)
#define HCR_APK		__HCR(APK)
#define HCR_TEA		__HCR(TEA)
#define HCR_TERR	__HCR(TERR)
#define HCR_TLOR	__HCR(TLOR)
#define HCR_E2H		__HCR(E2H)
#define HCR_ID		__HCR(ID)
#define HCR_CD		__HCR(CD)
#define HCR_RW		__HCR(RW)
#define HCR_TRVM	__HCR(TRVM)
#define HCR_HCD		__HCR(HCD)
#define HCR_TDZ		__HCR(TDZ)
#define HCR_TGE		__HCR(TGE)
#define HCR_TVM		__HCR(TVM)
#define HCR_TTLB	__HCR(TTLB)
#define HCR_TPU		__HCR(TPU)
#define HCR_TPC		__HCR(TPCP)
#define HCR_TSW		__HCR(TSW)
#define HCR_TACR	__HCR(TACR)
#define HCR_TIDCP	__HCR(TIDCP)
#define HCR_TSC		__HCR(TSC)
#define HCR_TID3	__HCR(TID3)
#define HCR_TID2	__HCR(TID2)
#define HCR_TID1	__HCR(TID1)
#define HCR_TID0	__HCR(TID0)
#define HCR_TWE		__HCR(TWE)
#define HCR_TWI		__HCR(TWI)
#define HCR_DC		__HCR(DC)
#define HCR_BSU		__HCR(BSU)
#define HCR_BSU_IS	__HCR(BSU_IS)
#define HCR_FB		__HCR(FB)
#define HCR_VSE		__HCR(VSE)
#define HCR_VI		__HCR(VI)
#define HCR_VF		__HCR(VF)
#define HCR_AMO		__HCR(AMO)
#define HCR_IMO		__HCR(IMO)
#define HCR_FMO		__HCR(FMO)
#define HCR_PTW		__HCR(PTW)
#define HCR_SWIO	__HCR(SWIO)
#define HCR_VM		__HCR(VM)

/*
 * The bits we set in HCR:
 * TLOR:	Trap LORegion register accesses
 * RW:		64bit by default, can be overridden for 32bit VMs
 * TACR:	Trap ACTLR
 * TSC:		Trap SMC
 * TSW:		Trap cache operations by set/way
 * TWE:		Trap WFE
 * TWI:		Trap WFI
 * TIDCP:	Trap L2CTLR/L2ECTLR
 * BSU_IS:	Upgrade barriers to the inner shareable domain
 * FB:		Force broadcast of all maintenance operations
 * AMO:		Override CPSR.A and enable signaling with VA
 * IMO:		Override CPSR.I and enable signaling with VI
 * FMO:		Override CPSR.F and enable signaling with VF
 * SWIO:	Turn set/way invalidates into set/way clean+invalidate
 * PTW:		Take a stage2 fault if a stage1 walk steps in device memory

Annotation

Implementation Notes