arch/arm64/include/asm/trans_pgd.h

File Facts

System

Linux kernel

Corpus path

arch/arm64/include/asm/trans_pgd.h

Extension

.h

Size

1041 bytes

Lines

42

Domain

Architecture Layer

Bucket

arch/arm64

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/bits.h
• linux/types.h
• asm/pgtable-types.h

Detected Declarations

• struct trans_pgd_info

Annotated Snippet

struct trans_pgd_info {
	void * (*trans_alloc_page)(void *arg);
	void *trans_alloc_arg;
};

int trans_pgd_create_copy(struct trans_pgd_info *info, pgd_t **trans_pgd,
			  unsigned long start, unsigned long end);

int trans_pgd_idmap_page(struct trans_pgd_info *info, phys_addr_t *trans_ttbr0,
			 unsigned long *t0sz, void *page);

int trans_pgd_copy_el2_vectors(struct trans_pgd_info *info,
			       phys_addr_t *el2_vectors);

extern char trans_pgd_stub_vectors[];

#endif /* _ASM_TRANS_TABLE_H */

Annotation

• Immediate include surface: `linux/bits.h`, `linux/types.h`, `asm/pgtable-types.h`.
• Detected declarations: `struct trans_pgd_info`.
• Atlas domain: Architecture Layer / arch/arm64.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.