arch/arm64/kvm/hyp/include/nvhe/arm-smccc.h
Source file repositories/reference/linux-study-clean/arch/arm64/kvm/hyp/include/nvhe/arm-smccc.h
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/kvm/hyp/include/nvhe/arm-smccc.h- Extension
.h- Size
- 621 bytes
- Lines
- 24
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
asm/kvm_hypevents.hlinux/arm-smccc.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __ARM64_KVM_HYP_NVHE_ARM_SMCCC_H__
#define __ARM64_KVM_HYP_NVHE_ARM_SMCCC_H__
#include <asm/kvm_hypevents.h>
#include <linux/arm-smccc.h>
#define hyp_smccc_1_1_smc(...) \
do { \
trace_hyp_exit(NULL, HYP_REASON_SMC); \
arm_smccc_1_1_smc(__VA_ARGS__); \
trace_hyp_enter(NULL, HYP_REASON_SMC); \
} while (0)
#define hyp_smccc_1_2_smc(...) \
do { \
trace_hyp_exit(NULL, HYP_REASON_SMC); \
arm_smccc_1_2_smc(__VA_ARGS__); \
trace_hyp_enter(NULL, HYP_REASON_SMC); \
} while (0)
#endif /* __ARM64_KVM_HYP_NVHE_ARM_SMCCC_H__ */
Annotation
- Immediate include surface: `asm/kvm_hypevents.h`, `linux/arm-smccc.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.