arch/arm64/kvm/hyp/vgic-v3-sr.c

Source file repositories/reference/linux-study-clean/arch/arm64/kvm/hyp/vgic-v3-sr.c

File Facts

System
Linux kernel
Corpus path
arch/arm64/kvm/hyp/vgic-v3-sr.c
Extension
.c
Size
28927 bytes
Lines
1290
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

if (!cpu_if->vgic_sre) {
			dsb(sy);
			isb();
		}
	}

	if (used_lrs) {
		int i;
		u32 elrsr;

		elrsr = read_gicreg(ICH_ELRSR_EL2);

		for (i = 0; i < used_lrs; i++) {
			if (elrsr & (1 << i))
				cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
			else
				cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);

			__gic_v3_set_lr(0, i);
		}
	}

	cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2);

	if (cpu_if->vgic_hcr & ICH_HCR_EL2_LRENPIE) {
		u64 val = read_gicreg(ICH_HCR_EL2);
		cpu_if->vgic_hcr &= ~ICH_HCR_EL2_EOIcount;
		cpu_if->vgic_hcr |= val & ICH_HCR_EL2_EOIcount;
	}

	write_gicreg(0, ICH_HCR_EL2);

	/*
	 * Hack alert: On NV, this results in a trap so that the above write
	 * actually takes effect... No synchronisation is necessary, as we
	 * only care about the effects when this traps.
	 */
	read_gicreg(ICH_MISR_EL2);
}

void __vgic_v3_restore_state(struct vgic_v3_cpu_if *cpu_if)
{
	u64 used_lrs = cpu_if->used_lrs;
	int i;

	write_gicreg(compute_ich_hcr(cpu_if), ICH_HCR_EL2);

	for (i = 0; i < used_lrs; i++)
		__gic_v3_set_lr(cpu_if->vgic_lr[i], i);

	/*
	 * Ensure that writes to the LRs, and on non-VHE systems ensure that
	 * the write to the VMCR in __vgic_v3_activate_traps(), will have
	 * reached the (re)distributors. This ensure the guest will read the
	 * correct values from the memory-mapped interface.
	 */
	if (used_lrs || !has_vhe()) {
		if (!cpu_if->vgic_sre) {
			isb();
			dsb(sy);
		}
	}
}

void __vgic_v3_activate_traps(struct vgic_v3_cpu_if *cpu_if)
{
	/*
	 * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
	 * Group0 interrupt (as generated in GICv2 mode) to be
	 * delivered as a FIQ to the guest, with potentially fatal
	 * consequences. So we must make sure that ICC_SRE_EL1 has
	 * been actually programmed with the value we want before
	 * starting to mess with the rest of the GIC, and VMCR_EL2 in
	 * particular.  This logic must be called before
	 * __vgic_v3_restore_state().
	 *
	 * However, if the vgic is disabled (ICH_HCR_EL2.EN==0), no GIC is
	 * provisioned at all. In order to prevent illegal accesses to the
	 * system registers to trap to EL1 (duh), force ICC_SRE_EL1.SRE to 1
	 * so that the trap bits can take effect. Yes, we *loves* the GIC.
	 */
	if (!(cpu_if->vgic_hcr & ICH_HCR_EL2_En)) {
		write_gicreg(ICC_SRE_EL1_SRE, ICC_SRE_EL1);
		isb();
	} else if (!cpu_if->vgic_sre) {
		write_gicreg(0, ICC_SRE_EL1);
		isb();
		write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);

Annotation

Implementation Notes