arch/csky/mm/cachev2.c

Source file repositories/reference/linux-study-clean/arch/csky/mm/cachev2.c

File Facts

System
Linux kernel
Corpus path
arch/csky/mm/cachev2.c
Extension
.c
Size
2692 bytes
Lines
121
Domain
Architecture Layer
Bucket
arch/csky
Inferred role
Architecture Layer: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cache_range {
	unsigned long start;
	unsigned long end;
};

static DEFINE_SPINLOCK(cache_lock);

static inline void cache_op_line(unsigned long i, unsigned int val)
{
	mtcr("cr22", i);
	mtcr("cr17", val);
}

void local_icache_inv_range(void *priv)
{
	struct cache_range *param = priv;
	unsigned long i = param->start & ~(L1_CACHE_BYTES - 1);
	unsigned long flags;

	spin_lock_irqsave(&cache_lock, flags);

	for (; i < param->end; i += L1_CACHE_BYTES)
		cache_op_line(i, INS_CACHE | CACHE_INV | CACHE_OMS);

	spin_unlock_irqrestore(&cache_lock, flags);

	sync_is();
}

void icache_inv_range(unsigned long start, unsigned long end)
{
	struct cache_range param = { start, end };

	if (irqs_disabled())
		local_icache_inv_range(&param);
	else
		on_each_cpu(local_icache_inv_range, &param, 1);
}
#endif

inline void dcache_wb_line(unsigned long start)
{
	asm volatile("dcache.cval1 %0\n"::"r"(start):"memory");
	sync_is();
}

void dcache_wb_range(unsigned long start, unsigned long end)
{
	unsigned long i = start & ~(L1_CACHE_BYTES - 1);

	for (; i < end; i += L1_CACHE_BYTES)
		asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
	sync_is();
}

void cache_wbinv_range(unsigned long start, unsigned long end)
{
	dcache_wb_range(start, end);
	icache_inv_range(start, end);
}
EXPORT_SYMBOL(cache_wbinv_range);

void dma_wbinv_range(unsigned long start, unsigned long end)
{
	unsigned long i = start & ~(L1_CACHE_BYTES - 1);

	for (; i < end; i += L1_CACHE_BYTES)
		asm volatile("dcache.civa %0\n"::"r"(i):"memory");
	sync_is();
}

void dma_inv_range(unsigned long start, unsigned long end)
{
	unsigned long i = start & ~(L1_CACHE_BYTES - 1);

	for (; i < end; i += L1_CACHE_BYTES)
		asm volatile("dcache.iva %0\n"::"r"(i):"memory");
	sync_is();
}

void dma_wb_range(unsigned long start, unsigned long end)
{
	unsigned long i = start & ~(L1_CACHE_BYTES - 1);

	for (; i < end; i += L1_CACHE_BYTES)
		asm volatile("dcache.cva %0\n"::"r"(i):"memory");
	sync_is();
}

Annotation

Implementation Notes