arch/csky/mm/tlb.c
Source file repositories/reference/linux-study-clean/arch/csky/mm/tlb.c
File Facts
- System
- Linux kernel
- Corpus path
arch/csky/mm/tlb.c- Extension
.c- Size
- 3635 bytes
- Lines
- 199
- Domain
- Architecture Layer
- Bucket
- arch/csky
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/mm.hlinux/module.hlinux/sched.hasm/mmu_context.hasm/setup.h
Detected Declarations
function flush_tlb_allfunction flush_tlb_mmfunction flush_tlb_rangefunction flush_tlb_kernel_rangefunction flush_tlb_pagefunction flush_tlb_oneexport flush_tlb_one
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <asm/mmu_context.h>
#include <asm/setup.h>
/*
* One C-SKY MMU TLB entry contain two PFN/page entry, ie:
* 1VPN -> 2PFN
*/
#define TLB_ENTRY_SIZE (PAGE_SIZE * 2)
#define TLB_ENTRY_SIZE_MASK (PAGE_MASK << 1)
void flush_tlb_all(void)
{
tlb_invalid_all();
}
void flush_tlb_mm(struct mm_struct *mm)
{
#ifdef CONFIG_CPU_HAS_TLBI
sync_is();
asm volatile(
"tlbi.asids %0 \n"
"sync.i \n"
:
: "r" (cpu_asid(mm))
: "memory");
#else
tlb_invalid_all();
#endif
}
/*
* MMU operation regs only could invalid tlb entry in jtlb and we
* need change asid field to invalid I-utlb & D-utlb.
*/
#ifndef CONFIG_CPU_HAS_TLBI
#define restore_asid_inv_utlb(oldpid, newpid) \
do { \
if (oldpid == newpid) \
write_mmu_entryhi(oldpid + 1); \
write_mmu_entryhi(oldpid); \
} while (0)
#endif
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
unsigned long newpid = cpu_asid(vma->vm_mm);
start &= TLB_ENTRY_SIZE_MASK;
end += TLB_ENTRY_SIZE - 1;
end &= TLB_ENTRY_SIZE_MASK;
#ifdef CONFIG_CPU_HAS_TLBI
sync_is();
while (start < end) {
asm volatile(
"tlbi.vas %0 \n"
:
: "r" (start | newpid)
: "memory");
start += 2*PAGE_SIZE;
}
asm volatile("sync.i\n");
#else
{
unsigned long flags, oldpid;
local_irq_save(flags);
oldpid = read_mmu_entryhi() & ASID_MASK;
while (start < end) {
int idx;
write_mmu_entryhi(start | newpid);
start += 2*PAGE_SIZE;
tlb_probe();
idx = read_mmu_index();
if (idx >= 0)
tlb_invalid_indexed();
}
restore_asid_inv_utlb(oldpid, newpid);
local_irq_restore(flags);
Annotation
- Immediate include surface: `linux/init.h`, `linux/mm.h`, `linux/module.h`, `linux/sched.h`, `asm/mmu_context.h`, `asm/setup.h`.
- Detected declarations: `function flush_tlb_all`, `function flush_tlb_mm`, `function flush_tlb_range`, `function flush_tlb_kernel_range`, `function flush_tlb_page`, `function flush_tlb_one`, `export flush_tlb_one`.
- Atlas domain: Architecture Layer / arch/csky.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.