arch/hexagon/include/asm/bitops.h
Source file repositories/reference/linux-study-clean/arch/hexagon/include/asm/bitops.h
File Facts
- System
- Linux kernel
- Corpus path
arch/hexagon/include/asm/bitops.h- Extension
.h- Size
- 6715 bytes
- Lines
- 305
- Domain
- Architecture Layer
- Bucket
- arch/hexagon
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
linux/compiler.hasm/byteorder.hasm/atomic.hasm/barrier.hasm-generic/bitops/lock.hasm-generic/bitops/non-instrumented-non-atomic.hasm-generic/bitops/fls64.hasm-generic/bitops/sched.hasm-generic/bitops/hweight.hasm-generic/bitops/le.hasm-generic/bitops/ext2-atomic.h
Detected Declarations
function Copyrightfunction test_and_set_bitfunction test_and_change_bitfunction clear_bitfunction set_bitfunction change_bitfunction arch___clear_bitfunction arch___set_bitfunction arch___change_bitfunction arch___test_and_clear_bitfunction arch___test_and_set_bitfunction arch___test_and_change_bitfunction arch_test_bitfunction arch_test_bit_acquirefunction ffzfunction flsfunction ffzfunction thinkfunction __fls
Annotated Snippet
#ifndef _ASM_BITOPS_H
#define _ASM_BITOPS_H
#include <linux/compiler.h>
#include <asm/byteorder.h>
#include <asm/atomic.h>
#include <asm/barrier.h>
#ifdef __KERNEL__
/*
* The offset calculations for these are based on BITS_PER_LONG == 32
* (i.e. I get to shift by #5-2 (32 bits per long, 4 bytes per access),
* mask by 0x0000001F)
*
* Typically, R10 is clobbered for address, R11 bit nr, and R12 is temp
*/
/**
* test_and_clear_bit - clear a bit and return its old value
* @nr: bit number to clear
* @addr: pointer to memory
*/
static inline int test_and_clear_bit(int nr, volatile void *addr)
{
int oldval;
__asm__ __volatile__ (
" {R10 = %1; R11 = asr(%2,#5); }\n"
" {R10 += asl(R11,#2); R11 = and(%2,#0x1f)}\n"
"1: R12 = memw_locked(R10);\n"
" { P0 = tstbit(R12,R11); R12 = clrbit(R12,R11); }\n"
" memw_locked(R10,P1) = R12;\n"
" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
: "=&r" (oldval)
: "r" (addr), "r" (nr)
: "r10", "r11", "r12", "p0", "p1", "memory"
);
return oldval;
}
/**
* test_and_set_bit - set a bit and return its old value
* @nr: bit number to set
* @addr: pointer to memory
*/
static inline int test_and_set_bit(int nr, volatile void *addr)
{
int oldval;
__asm__ __volatile__ (
" {R10 = %1; R11 = asr(%2,#5); }\n"
" {R10 += asl(R11,#2); R11 = and(%2,#0x1f)}\n"
"1: R12 = memw_locked(R10);\n"
" { P0 = tstbit(R12,R11); R12 = setbit(R12,R11); }\n"
" memw_locked(R10,P1) = R12;\n"
" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
: "=&r" (oldval)
: "r" (addr), "r" (nr)
: "r10", "r11", "r12", "p0", "p1", "memory"
);
return oldval;
}
/**
* test_and_change_bit - toggle a bit and return its old value
* @nr: bit number to set
* @addr: pointer to memory
*/
static inline int test_and_change_bit(int nr, volatile void *addr)
{
int oldval;
__asm__ __volatile__ (
" {R10 = %1; R11 = asr(%2,#5); }\n"
" {R10 += asl(R11,#2); R11 = and(%2,#0x1f)}\n"
"1: R12 = memw_locked(R10);\n"
" { P0 = tstbit(R12,R11); R12 = togglebit(R12,R11); }\n"
" memw_locked(R10,P1) = R12;\n"
" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
: "=&r" (oldval)
: "r" (addr), "r" (nr)
: "r10", "r11", "r12", "p0", "p1", "memory"
);
return oldval;
Annotation
- Immediate include surface: `linux/compiler.h`, `asm/byteorder.h`, `asm/atomic.h`, `asm/barrier.h`, `asm-generic/bitops/lock.h`, `asm-generic/bitops/non-instrumented-non-atomic.h`, `asm-generic/bitops/fls64.h`, `asm-generic/bitops/sched.h`.
- Detected declarations: `function Copyright`, `function test_and_set_bit`, `function test_and_change_bit`, `function clear_bit`, `function set_bit`, `function change_bit`, `function arch___clear_bit`, `function arch___set_bit`, `function arch___change_bit`, `function arch___test_and_clear_bit`.
- Atlas domain: Architecture Layer / arch/hexagon.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.