arch/hexagon/include/asm/cmpxchg.h
Source file repositories/reference/linux-study-clean/arch/hexagon/include/asm/cmpxchg.h
File Facts
- System
- Linux kernel
- Corpus path
arch/hexagon/include/asm/cmpxchg.h- Extension
.h- Size
- 2020 bytes
- Lines
- 76
- Domain
- Architecture Layer
- Bucket
- arch/hexagon
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
function Copyright
Annotated Snippet
#ifndef _ASM_CMPXCHG_H
#define _ASM_CMPXCHG_H
/*
* __arch_xchg - atomically exchange a register and a memory location
* @x: value to swap
* @ptr: pointer to memory
* @size: size of the value
*
* Only 4 bytes supported currently.
*
* Note: there was an errata for V2 about .new's and memw_locked.
*
*/
static inline unsigned long
__arch_xchg(unsigned long x, volatile void *ptr, int size)
{
unsigned long retval;
/* Can't seem to use printk or panic here, so just stop */
if (size != 4) do { asm volatile("brkpt;\n"); } while (1);
__asm__ __volatile__ (
"1: %0 = memw_locked(%1);\n" /* load into retval */
" memw_locked(%1,P0) = %2;\n" /* store into memory */
" if (!P0) jump 1b;\n"
: "=&r" (retval)
: "r" (ptr), "r" (x)
: "memory", "p0"
);
return retval;
}
/*
* Atomically swap the contents of a register with memory. Should be atomic
* between multiple CPU's and within interrupts on the same CPU.
*/
#define arch_xchg(ptr, v) ((__typeof__(*(ptr)))__arch_xchg((unsigned long)(v), (ptr), \
sizeof(*(ptr))))
/*
* see rt-mutex-design.txt; cmpxchg supposedly checks if *ptr == A and swaps.
* looks just like atomic_cmpxchg on our arch currently with a bunch of
* variable casting.
*/
#define arch_cmpxchg(ptr, old, new) \
({ \
__typeof__(ptr) __ptr = (ptr); \
__typeof__(*(ptr)) __old = (old); \
__typeof__(*(ptr)) __new = (new); \
__typeof__(*(ptr)) __oldval = (__typeof__(*(ptr))) 0; \
\
asm volatile( \
"1: %0 = memw_locked(%1);\n" \
" { P0 = cmp.eq(%0,%2);\n" \
" if (!P0.new) jump:nt 2f; }\n" \
" memw_locked(%1,p0) = %3;\n" \
" if (!P0) jump 1b;\n" \
"2:\n" \
: "=&r" (__oldval) \
: "r" (__ptr), "r" (__old), "r" (__new) \
: "memory", "p0" \
); \
__oldval; \
})
#endif /* _ASM_CMPXCHG_H */
Annotation
- Detected declarations: `function Copyright`.
- Atlas domain: Architecture Layer / arch/hexagon.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.