arch/hexagon/include/asm/hexagon_vm.h
Source file repositories/reference/linux-study-clean/arch/hexagon/include/asm/hexagon_vm.h
File Facts
- System
- Linux kernel
- Corpus path
arch/hexagon/include/asm/hexagon_vm.h- Extension
.h- Size
- 5909 bytes
- Lines
- 277
- Domain
- Architecture Layer
- Bucket
- arch/hexagon
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
enum VM_CACHE_OPSenum VM_INT_OPSfunction __vmcache_ickillfunction __vmcache_dckillfunction __vmcache_l2killfunction __vmcache_dccleaninvafunction __vmcache_icinvafunction __vmcache_idsyncfunction __vmcache_fetch_cfgfunction __vmintop_nopfunction __vmintop_globenfunction __vmintop_globdisfunction __vmintop_locenfunction __vmintop_locdisfunction __vmintop_affinityfunction __vmintop_getfunction __vmintop_peekfunction __vmintop_statusfunction __vmintop_postfunction __vmintop_clear
Annotated Snippet
#ifndef ASM_HEXAGON_VM_H
#define ASM_HEXAGON_VM_H
/*
* In principle, a Linux kernel for the VM could
* selectively define the virtual instructions
* as inline assembler macros, but for a first pass,
* we'll use subroutines for both the VM and the native
* kernels. It's costing a subroutine call/return,
* but it makes for a single set of entry points
* for tracing/debugging.
*/
#define HVM_TRAP1_VMVERSION 0
#define HVM_TRAP1_VMRTE 1
#define HVM_TRAP1_VMSETVEC 2
#define HVM_TRAP1_VMSETIE 3
#define HVM_TRAP1_VMGETIE 4
#define HVM_TRAP1_VMINTOP 5
#define HVM_TRAP1_VMCLRMAP 10
#define HVM_TRAP1_VMNEWMAP 11
#define HVM_TRAP1_FORMERLY_VMWIRE 12
#define HVM_TRAP1_VMCACHE 13
#define HVM_TRAP1_VMGETTIME 14
#define HVM_TRAP1_VMSETTIME 15
#define HVM_TRAP1_VMWAIT 16
#define HVM_TRAP1_VMYIELD 17
#define HVM_TRAP1_VMSTART 18
#define HVM_TRAP1_VMSTOP 19
#define HVM_TRAP1_VMVPID 20
#define HVM_TRAP1_VMSETREGS 21
#define HVM_TRAP1_VMGETREGS 22
#define HVM_TRAP1_VMTIMEROP 24
#ifndef __ASSEMBLY__
enum VM_CACHE_OPS {
hvmc_ickill,
hvmc_dckill,
hvmc_l2kill,
hvmc_dccleaninva,
hvmc_icinva,
hvmc_idsync,
hvmc_fetch_cfg
};
enum VM_INT_OPS {
hvmi_nop,
hvmi_globen,
hvmi_globdis,
hvmi_locen,
hvmi_locdis,
hvmi_affinity,
hvmi_get,
hvmi_peek,
hvmi_status,
hvmi_post,
hvmi_clear
};
extern void _K_VM_event_vector(void);
void __vmrte(void);
long __vmsetvec(void *);
long __vmsetie(long);
long __vmgetie(void);
long __vmintop(enum VM_INT_OPS, long, long, long, long);
long __vmclrmap(void *, unsigned long);
long __vmnewmap(void *);
long __vmcache(enum VM_CACHE_OPS op, unsigned long addr, unsigned long len);
unsigned long long __vmgettime(void);
long __vmsettime(unsigned long long);
long __vmstart(void *, void *);
void __vmstop(void);
long __vmwait(void);
void __vmyield(void);
long __vmvpid(void);
static inline long __vmcache_ickill(void)
{
return __vmcache(hvmc_ickill, 0, 0);
}
static inline long __vmcache_dckill(void)
{
return __vmcache(hvmc_dckill, 0, 0);
}
static inline long __vmcache_l2kill(void)
{
Annotation
- Detected declarations: `enum VM_CACHE_OPS`, `enum VM_INT_OPS`, `function __vmcache_ickill`, `function __vmcache_dckill`, `function __vmcache_l2kill`, `function __vmcache_dccleaninva`, `function __vmcache_icinva`, `function __vmcache_idsync`, `function __vmcache_fetch_cfg`, `function __vmintop_nop`.
- Atlas domain: Architecture Layer / arch/hexagon.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.