arch/hexagon/mm/cache.c
Source file repositories/reference/linux-study-clean/arch/hexagon/mm/cache.c
File Facts
- System
- Linux kernel
- Corpus path
arch/hexagon/mm/cache.c- Extension
.c- Size
- 2400 bytes
- Lines
- 127
- Domain
- Architecture Layer
- Bucket
- arch/hexagon
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/mm.hasm/cacheflush.hasm/hexagon_vm.h
Detected Declarations
function Copyrightfunction flush_icache_rangefunction hexagon_clean_dcache_rangefunction hexagon_inv_dcache_rangefunction flush_cache_all_hexagonfunction copy_to_user_pageexport flush_icache_range
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Cache management functions for Hexagon
*
* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
*/
#include <linux/mm.h>
#include <asm/cacheflush.h>
#include <asm/hexagon_vm.h>
#define spanlines(start, end) \
(((end - (start & ~(LINESIZE - 1))) >> LINEBITS) + 1)
void flush_dcache_range(unsigned long start, unsigned long end)
{
unsigned long lines = spanlines(start, end-1);
unsigned long i, flags;
start &= ~(LINESIZE - 1);
local_irq_save(flags);
for (i = 0; i < lines; i++) {
__asm__ __volatile__ (
" dccleaninva(%0); "
:
: "r" (start)
);
start += LINESIZE;
}
local_irq_restore(flags);
}
void flush_icache_range(unsigned long start, unsigned long end)
{
unsigned long lines = spanlines(start, end-1);
unsigned long i, flags;
start &= ~(LINESIZE - 1);
local_irq_save(flags);
for (i = 0; i < lines; i++) {
__asm__ __volatile__ (
" dccleana(%0); "
" icinva(%0); "
:
: "r" (start)
);
start += LINESIZE;
}
__asm__ __volatile__ (
"isync"
);
local_irq_restore(flags);
}
EXPORT_SYMBOL(flush_icache_range);
void hexagon_clean_dcache_range(unsigned long start, unsigned long end)
{
unsigned long lines = spanlines(start, end-1);
unsigned long i, flags;
start &= ~(LINESIZE - 1);
local_irq_save(flags);
for (i = 0; i < lines; i++) {
__asm__ __volatile__ (
" dccleana(%0); "
:
: "r" (start)
);
start += LINESIZE;
}
local_irq_restore(flags);
}
void hexagon_inv_dcache_range(unsigned long start, unsigned long end)
{
unsigned long lines = spanlines(start, end-1);
unsigned long i, flags;
start &= ~(LINESIZE - 1);
local_irq_save(flags);
for (i = 0; i < lines; i++) {
__asm__ __volatile__ (
Annotation
- Immediate include surface: `linux/mm.h`, `asm/cacheflush.h`, `asm/hexagon_vm.h`.
- Detected declarations: `function Copyright`, `function flush_icache_range`, `function hexagon_clean_dcache_range`, `function hexagon_inv_dcache_range`, `function flush_cache_all_hexagon`, `function copy_to_user_page`, `export flush_icache_range`.
- Atlas domain: Architecture Layer / arch/hexagon.
- Implementation status: integration implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.