arch/hexagon/mm/vm_tlb.c
Source file repositories/reference/linux-study-clean/arch/hexagon/mm/vm_tlb.c
File Facts
- System
- Linux kernel
- Corpus path
arch/hexagon/mm/vm_tlb.c- Extension
.c- Size
- 2250 bytes
- Lines
- 83
- Domain
- Architecture Layer
- Bucket
- arch/hexagon
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/mm.hlinux/sched.hasm/page.hasm/hexagon_vm.hasm/tlbflush.h
Detected Declarations
function Copyrightfunction flush_tlb_onefunction tlb_flush_allfunction flush_tlb_mmfunction flush_tlb_pagefunction flush_tlb_kernel_range
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Hexagon Virtual Machine TLB functions
*
* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
*/
/*
* The Hexagon Virtual Machine conceals the real workings of
* the TLB, but there are one or two functions that need to
* be instantiated for it, differently from a native build.
*/
#include <linux/mm.h>
#include <linux/sched.h>
#include <asm/page.h>
#include <asm/hexagon_vm.h>
#include <asm/tlbflush.h>
/*
* Initial VM implementation has only one map active at a time, with
* TLB purgings on changes. So either we're nuking the current map,
* or it's a no-op. This operation is messy on true SMPs where other
* processors must be induced to flush the copies in their local TLBs,
* but Hexagon thread-based virtual processors share the same MMU.
*/
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
struct mm_struct *mm = vma->vm_mm;
if (mm->context.ptbase == current->active_mm->context.ptbase)
__vmclrmap((void *)start, end - start);
}
/*
* Flush a page from the kernel virtual map - used by highmem
*/
void flush_tlb_one(unsigned long vaddr)
{
__vmclrmap((void *)vaddr, PAGE_SIZE);
}
/*
* Flush all TLBs across all CPUs, virtual or real.
* A single Hexagon core has 6 thread contexts but
* only one TLB.
*/
void tlb_flush_all(void)
{
/* should probably use that fixaddr end or whateve label */
__vmclrmap(0, 0xffff0000);
}
/*
* Flush TLB entries associated with a given mm_struct mapping.
*/
void flush_tlb_mm(struct mm_struct *mm)
{
/* Current Virtual Machine has only one map active at a time */
if (current->active_mm->context.ptbase == mm->context.ptbase)
tlb_flush_all();
}
/*
* Flush TLB state associated with a page of a vma.
*/
void flush_tlb_page(struct vm_area_struct *vma, unsigned long vaddr)
{
struct mm_struct *mm = vma->vm_mm;
if (mm->context.ptbase == current->active_mm->context.ptbase)
__vmclrmap((void *)vaddr, PAGE_SIZE);
}
/*
* Flush TLB entries associated with a kernel address range.
* Like flush range, but without the check on the vma->vm_mm.
*/
void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
__vmclrmap((void *)start, end - start);
}
Annotation
- Immediate include surface: `linux/mm.h`, `linux/sched.h`, `asm/page.h`, `asm/hexagon_vm.h`, `asm/tlbflush.h`.
- Detected declarations: `function Copyright`, `function flush_tlb_one`, `function tlb_flush_all`, `function flush_tlb_mm`, `function flush_tlb_page`, `function flush_tlb_kernel_range`.
- Atlas domain: Architecture Layer / arch/hexagon.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.