arch/loongarch/include/asm/stackframe.h

Source file repositories/reference/linux-study-clean/arch/loongarch/include/asm/stackframe.h

File Facts

System
Linux kernel
Corpus path
arch/loongarch/include/asm/stackframe.h
Extension
.h
Size
6189 bytes
Lines
273
Domain
Architecture Layer
Bucket
arch/loongarch
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ASM_STACKFRAME_H
#define _ASM_STACKFRAME_H

#include <linux/threads.h>

#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/asm-offsets.h>
#include <asm/loongarch.h>
#include <asm/thread_info.h>
#include <asm/unwind_hints.h>

/* Make the addition of cfi info a little easier. */
	.macro cfi_rel_offset reg offset=0 docfi=0
	.if \docfi
	.cfi_rel_offset \reg, \offset
	.endif
	.endm

	.macro cfi_st reg offset=0 docfi=0
	cfi_rel_offset \reg, \offset, \docfi
	LONG_S	\reg, sp, \offset
	.endm

	.macro cfi_restore reg offset=0 docfi=0
	.if \docfi
	.cfi_restore \reg
	.endif
	.endm

	.macro cfi_ld reg offset=0 docfi=0
	LONG_L	\reg, sp, \offset
	cfi_restore \reg \offset \docfi
	.endm

	.macro SETUP_TWINS temp
	pcaddi	t0, 0
	PTR_LI	t1, ~TO_PHYS_MASK
	and	t0, t0, t1
	ori	t0, t0, (1 << 4 | 1)
	csrwr	t0, LOONGARCH_CSR_DMWIN0
	PTR_LI	t0, CSR_DMW1_INIT
	csrwr	t0, LOONGARCH_CSR_DMWIN1
	.endm

	.macro SETUP_MODES temp
	/* Enable PG */
	li.w	\temp, 0xb0		# PLV=0, IE=0, PG=1
	csrwr	\temp, LOONGARCH_CSR_CRMD
	li.w	\temp, 0x04		# PLV=0, PIE=1, PWE=0
	csrwr	\temp, LOONGARCH_CSR_PRMD
	li.w	\temp, 0x00		# FPE=0, SXE=0, ASXE=0, BTE=0
	csrwr	\temp, LOONGARCH_CSR_EUEN
	.endm

	.macro SETUP_DMWINS temp
	PTR_LI	\temp, CSR_DMW0_INIT	# SUC, PLV0, LA32: 0x8xxx xxxx, LA64: 0x8000 xxxx xxxx xxxx
	csrwr	\temp, LOONGARCH_CSR_DMWIN0
	PTR_LI	\temp, CSR_DMW1_INIT	# CAC, PLV0, LA32: 0xaxxx xxxx, LA64: 0x9000 xxxx xxxx xxxx
	csrwr	\temp, LOONGARCH_CSR_DMWIN1
	PTR_LI	\temp, CSR_DMW2_INIT	# WUC, PLV0, LA32: unavailable, LA64: 0xa000 xxxx xxxx xxxx
	csrwr	\temp, LOONGARCH_CSR_DMWIN2
	PTR_LI	\temp, CSR_DMW3_INIT	# 0x0, unused
	csrwr	\temp, LOONGARCH_CSR_DMWIN3
	.endm

/* Jump to the runtime virtual address. */
	.macro JUMP_VIRT_ADDR temp1 temp2
	PTR_LI	\temp1, CACHE_BASE
	pcaddi	\temp2, 0
	PTR_BSTRINS  \temp1, \temp2, (DMW_PABITS - 1), 0
	jirl	zero, \temp1, 0xc
	.endm

	.macro STACKLEAK_ERASE
#ifdef CONFIG_KSTACK_ERASE
	bl	stackleak_erase_on_task_stack
#endif
	.endm

	.macro BACKUP_T0T1
	csrwr	t0, EXCEPTION_KS0
	csrwr	t1, EXCEPTION_KS1
	.endm

	.macro RELOAD_T0T1
	csrrd   t0, EXCEPTION_KS0
	csrrd   t1, EXCEPTION_KS1
	.endm

Annotation

Implementation Notes