arch/loongarch/kernel/inst.c
Source file repositories/reference/linux-study-clean/arch/loongarch/kernel/inst.c
File Facts
- System
- Linux kernel
- Corpus path
arch/loongarch/kernel/inst.c- Extension
.c- Size
- 9818 bytes
- Lines
- 444
- Domain
- Architecture Layer
- Bucket
- arch/loongarch
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/sizes.hlinux/uaccess.hlinux/set_memory.hlinux/stop_machine.hasm/cacheflush.hasm/inst.h
Detected Declarations
struct insn_copyfunction simu_pcfunction simu_branchfunction insns_not_supportedfunction insns_need_simulationfunction arch_simulate_insnfunction larch_insn_readfunction larch_insn_writefunction larch_insn_patch_textfunction text_copy_cbfunction larch_insn_text_copyfunction larch_insn_gen_nopfunction larch_insn_gen_bfunction larch_insn_gen_blfunction larch_insn_gen_breakfunction larch_insn_gen_orfunction larch_insn_gen_movefunction larch_insn_gen_lu12iwfunction larch_insn_gen_lu32idfunction larch_insn_gen_lu52idfunction larch_insn_gen_beqfunction larch_insn_gen_bnefunction larch_insn_gen_jirl
Annotated Snippet
struct insn_copy {
void *dst;
void *src;
size_t len;
unsigned int cpu;
};
static int text_copy_cb(void *data)
{
int ret = 0;
struct insn_copy *copy = data;
if (smp_processor_id() == copy->cpu) {
ret = copy_to_kernel_nofault(copy->dst, copy->src, copy->len);
if (ret) {
pr_err("%s: operation failed\n", __func__);
return ret;
}
}
flush_icache_range((unsigned long)copy->dst, (unsigned long)copy->dst + copy->len);
return 0;
}
int larch_insn_text_copy(void *dst, void *src, size_t len)
{
int ret = 0;
int err = 0;
size_t start, end;
struct insn_copy copy = {
.dst = dst,
.src = src,
.len = len,
.cpu = raw_smp_processor_id(),
};
/*
* Ensure copy.cpu won't be hot removed before stop_machine.
* If it is removed nobody will really update the text.
*/
lockdep_assert_cpus_held();
start = round_down((size_t)dst, PAGE_SIZE);
end = round_up((size_t)dst + len, PAGE_SIZE);
err = set_memory_rw(start, (end - start) / PAGE_SIZE);
if (err) {
pr_info("%s: set_memory_rw() failed\n", __func__);
return err;
}
ret = stop_machine_cpuslocked(text_copy_cb, ©, cpu_online_mask);
err = set_memory_rox(start, (end - start) / PAGE_SIZE);
if (err) {
pr_info("%s: set_memory_rox() failed\n", __func__);
return err;
}
return ret;
}
u32 larch_insn_gen_nop(void)
{
return INSN_NOP;
}
u32 larch_insn_gen_b(unsigned long pc, unsigned long dest)
{
long offset = dest - pc;
union loongarch_instruction insn;
if ((offset & 3) || offset < -SZ_128M || offset >= SZ_128M) {
pr_warn("The generated b instruction is out of range.\n");
return INSN_BREAK;
}
emit_b(&insn, offset >> 2);
return insn.word;
}
u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest)
{
long offset = dest - pc;
union loongarch_instruction insn;
if ((offset & 3) || offset < -SZ_128M || offset >= SZ_128M) {
pr_warn("The generated bl instruction is out of range.\n");
Annotation
- Immediate include surface: `linux/sizes.h`, `linux/uaccess.h`, `linux/set_memory.h`, `linux/stop_machine.h`, `asm/cacheflush.h`, `asm/inst.h`.
- Detected declarations: `struct insn_copy`, `function simu_pc`, `function simu_branch`, `function insns_not_supported`, `function insns_need_simulation`, `function arch_simulate_insn`, `function larch_insn_read`, `function larch_insn_write`, `function larch_insn_patch_text`, `function text_copy_cb`.
- Atlas domain: Architecture Layer / arch/loongarch.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.