arch/loongarch/kernel/smp.c
Source file repositories/reference/linux-study-clean/arch/loongarch/kernel/smp.c
File Facts
- System
- Linux kernel
- Corpus path
arch/loongarch/kernel/smp.c- Extension
.c- Size
- 19656 bytes
- Lines
- 857
- Domain
- Architecture Layer
- Bucket
- arch/loongarch
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/acpi.hlinux/cpu.hlinux/cpumask.hlinux/init.hlinux/interrupt.hlinux/irq_work.hlinux/profile.hlinux/seq_file.hlinux/smp.hlinux/threads.hlinux/export.hlinux/suspend.hlinux/syscore_ops.hlinux/time.hlinux/tracepoint.hlinux/sched/hotplug.hlinux/sched/task_stack.hasm/cpu.hasm/idle.hasm/loongson.hasm/mmu_context.hasm/numa.hasm/paravirt.hasm/processor.hasm/setup.hasm/time.h
Detected Declarations
struct flush_tlb_datafunction show_ipi_listfunction set_cpu_core_mapfunction for_each_cpufunction set_cpu_llc_shared_mapfunction for_each_cpufunction clear_cpu_llc_shared_mapfunction for_each_cpufunction set_cpu_sibling_mapfunction for_each_cpufunction clear_cpu_sibling_mapfunction for_each_cpufunction calculate_cpu_foreign_mapfunction csr_mail_sendfunction ipi_read_clearfunction ipi_write_actionfunction loongson_send_ipi_singlefunction loongson_send_ipi_maskfunction arch_smp_send_reschedulefunction arch_irq_work_raisefunction loongson_ipi_interruptfunction loongson_init_ipifunction fdt_smp_setupfunction for_each_of_cpu_nodefunction loongson_smp_setupfunction loongson_prepare_cpusfunction for_each_possible_cpufunction loongson_boot_secondaryfunction loongson_init_secondaryfunction loongson_smp_finishfunction loongson_cpu_disablefunction loongson_cpu_diefunction idle_play_deadfunction poll_play_deadfunction arch_cpu_idle_deadfunction hibernate_resume_nonboot_cpu_disablefunction loongson_ipi_suspendfunction loongson_ipi_resumefunction ipi_pm_initfunction smp_prepare_boot_cpufunction smp_prepare_cpusfunction __cpu_upfunction msecs_to_jiffiesfunction start_secondaryfunction smp_cpus_donefunction smp_send_stopfunction setup_profiling_timerfunction flush_tlb_all_ipi
Annotated Snippet
core_initcall(ipi_pm_init);
#endif
/* Preload SMP state for boot cpu */
void __init smp_prepare_boot_cpu(void)
{
unsigned int cpu, node, rr_node;
set_cpu_possible(0, true);
set_cpu_online(0, true);
set_my_cpu_offset(per_cpu_offset(0));
numa_add_cpu(0);
rr_node = first_node(node_online_map);
for_each_possible_cpu(cpu) {
node = early_cpu_to_node(cpu);
/*
* The mapping between present cpus and nodes has been
* built during MADT and SRAT parsing.
*
* If possible cpus = present cpus here, early_cpu_to_node
* will return valid node.
*
* If possible cpus > present cpus here (e.g. some possible
* cpus will be added by cpu-hotplug later), for possible but
* not present cpus, early_cpu_to_node will return NUMA_NO_NODE,
* and we just map them to online nodes in round-robin way.
* Once hotplugged, new correct mapping will be built for them.
*/
if (node != NUMA_NO_NODE)
set_cpu_numa_node(cpu, node);
else {
set_cpu_numa_node(cpu, rr_node);
rr_node = next_node_in(rr_node, node_online_map);
}
}
pv_spinlock_init();
}
/* called from main before smp_init() */
void __init smp_prepare_cpus(unsigned int max_cpus)
{
init_new_context(current, &init_mm);
current_thread_info()->cpu = 0;
loongson_prepare_cpus(max_cpus);
set_cpu_sibling_map(0);
set_cpu_llc_shared_map(0);
set_cpu_core_map(0);
calculate_cpu_foreign_map();
#ifndef CONFIG_HOTPLUG_CPU
init_cpu_present(cpu_possible_mask);
#endif
}
int __cpu_up(unsigned int cpu, struct task_struct *tidle)
{
loongson_boot_secondary(cpu, tidle);
/* Wait for CPU to start and be ready to sync counters */
if (!wait_for_completion_timeout(&cpu_starting,
msecs_to_jiffies(5000))) {
pr_crit("CPU%u: failed to start\n", cpu);
return -EIO;
}
/* Wait for CPU to finish startup & mark itself online before return */
wait_for_completion(&cpu_running);
return 0;
}
/*
* First C code run on the secondary CPUs after being started up by
* the master.
*/
asmlinkage void start_secondary(void)
{
unsigned int cpu;
sync_counter();
cpu = raw_smp_processor_id();
set_my_cpu_offset(per_cpu_offset(cpu));
cpu_probe();
constant_clockevent_init();
loongson_init_secondary();
set_cpu_sibling_map(cpu);
Annotation
- Immediate include surface: `linux/acpi.h`, `linux/cpu.h`, `linux/cpumask.h`, `linux/init.h`, `linux/interrupt.h`, `linux/irq_work.h`, `linux/profile.h`, `linux/seq_file.h`.
- Detected declarations: `struct flush_tlb_data`, `function show_ipi_list`, `function set_cpu_core_map`, `function for_each_cpu`, `function set_cpu_llc_shared_map`, `function for_each_cpu`, `function clear_cpu_llc_shared_map`, `function for_each_cpu`, `function set_cpu_sibling_map`, `function for_each_cpu`.
- Atlas domain: Architecture Layer / arch/loongarch.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.