arch/m68k/coldfire/intc.c

Source file repositories/reference/linux-study-clean/arch/m68k/coldfire/intc.c

File Facts

System
Linux kernel
Corpus path
arch/m68k/coldfire/intc.c
Extension
.c
Size
3512 bytes
Lines
151
Domain
Architecture Layer
Bucket
arch/m68k
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/traps.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>

/*
 * The mapping of irq number to a mask register bit is not one-to-one.
 * The irq numbers are either based on "level" of interrupt or fixed
 * for an autovector-able interrupt. So we keep a local data structure
 * that maps from irq to mask register. Not all interrupts will have
 * an IMR bit.
 */
unsigned char mcf_irq2imr[NR_IRQS];

/*
 * Define the minimum and maximum external interrupt numbers.
 * This is also used as the "level" interrupt numbers.
 */
#define	EIRQ1	25
#define	EIRQ7	31

/*
 * In the early version 2 core ColdFire parts the IMR register was 16 bits
 * in size. Version 3 (and later version 2) core parts have a 32 bit
 * sized IMR register. Provide some size independent methods to access the
 * IMR register.
 */
#ifdef MCFSIM_IMR_IS_16BITS

void mcf_setimr(int index)
{
	u16 imr;
	imr = mcf_read16(MCFSIM_IMR);
	mcf_write16(imr | (0x1 << index), MCFSIM_IMR);
}

void mcf_clrimr(int index)
{
	u16 imr;
	imr = mcf_read16(MCFSIM_IMR);
	mcf_write16(imr & ~(0x1 << index), MCFSIM_IMR);
}

static void mcf_maskimr(unsigned int mask)
{
	u16 imr;
	imr = mcf_read16(MCFSIM_IMR);
	imr |= mask;
	mcf_write16(imr, MCFSIM_IMR);
}

#else

void mcf_setimr(int index)
{
	u32 imr;
	imr = mcf_read32(MCFSIM_IMR);
	mcf_write32(imr | (0x1 << index), MCFSIM_IMR);
}

void mcf_clrimr(int index)
{
	u32 imr;
	imr = mcf_read32(MCFSIM_IMR);
	mcf_write32(imr & ~(0x1 << index), MCFSIM_IMR);
}

static void mcf_maskimr(unsigned int mask)
{
	u32 imr;
	imr = mcf_read32(MCFSIM_IMR);
	imr |= mask;
	mcf_write32(imr, MCFSIM_IMR);
}

#endif

/*
 * Interrupts can be "vectored" on the ColdFire cores that support this old
 * interrupt controller. That is, the device raising the interrupt can also
 * supply the vector number to interrupt through. The AVR register of the
 * interrupt controller enables or disables this for each external interrupt,
 * so provide generic support for this. Setting this up is out-of-band for
 * the interrupt system API's, and needs to be done by the driver that
 * supports this device. Very few devices actually use this.

Annotation

Implementation Notes